The present invention relates to a redundant decoder circuit, and more particularly to a redundant decoder circuit to a memory selecting circuit executing continuous accesses by multi-bit pre-fetch. Recently, operating speed of CPU has been on the remarkable increase. On the other hand, a main memory such as dynamic random access memory is slower in operating speed than CPU due to a large capacity of the main memory. For those reasons, a cache memory may be used which is provided between CPU and the main memory. The cache memory is smaller in capacity but much faster in operating or access speed than the main memory. The use of such cache memory realizes a high speed and large capacity memory equivalently. CPU on execution of programs is made to have access to the cache memory. Hit ratios when the cache memory is used may be increased to about 90% so that CPU can fetch data from the cache memory at 90% probability with a requirement for access to the main memory at 10% probability. In accordance with the experimental law that instructions stored at addresses around an address, where the used instruction has been just stored, are likely to be used at a high probability, a currently required instruction is first read out from a designated address for subsequent read out of non-required instructions from addresses different only in lower bit from the above designated address so that both the required and non-required instructions are stored in the cache memory. Therefore, the main memory is capable of allowing that the required data are first read out from the designated address and subsequently non-required data are read out from the addresses different only in lower bit from the designated address. Nibble mode access or 2-bit pre-fetch access have been known as the sequential accesses. Notwithstanding, those accesses need many data latch circuits and buses. It is also difficult to make sequential accesses from an odd address.
In the Japanese laid-open patent publication No. 6-146349, it is disclosed that a memory selective circuit is provided for n-bit pre-fetch sequential accesses wherein a plurality of column lines are multiply selected, each of which is to select only an address of data to be outputted in one output timing.
In the above system, upon receipt of information of input address and burst length which means a length of data to be sequentially outputted, a column selective line corresponding to the input address and another column selective line corresponding to another address of data to be outputted are multiply selected.
As described above, in the conventional system, the single column selective line can select only an address of data to be outputted in one output timing, for which reason even if the plural column selective lines are currently selected and a pre-fetch system is utilized to output data separately in plural times, then it is possible to combine optionally data to be pre-fetched. There is no limitation to the order in outputting the data. For those reasons, it is possible to make sequential accesses from the odd address.
The above memory selecting circuit will further be described in more detail. The memory selecting circuit is provided with a pre-fetch decoder for decoding lower bits of the column address. The pre-fetch decoder receives not only an address but also information which indicates burst length for supplying a column decoder with a pre-decode address to activate two bits of the address. The column decoder then receives the pre-decode address and the remaining higher bits of the column address to select concurrently two column selective lines connected to memory cells from which data are required to be read out, so that the data corresponding to the two time outputs are concurrently read out.
FIG. 1 is a circuit diagram illustrative of a conventional 16M-bit DRAM 1000 integrated on a semiconductor chip. The 16M-bit DRAM 1000 has a 16M-bit memory cell array 101 which has 4096 word lines and 512 column selective lines (CSL0-CSL511) so that one address corresponds to 8 memory cells and 8 bits signals are dealt with. The 16M-bit DRAM 1000 also has an address buffer 102 for receiving address informations and a row decoder 103 connected to the address buffer 102 for receiving the address signal from the address buffer 102 to decode the received address signal. The row decoder 103 is also connected to the memory cell array 101 for supplying the decoded address signals to the memory cell array to read out the data stored at the address in the memory cell array.
The 1.6 M-bit DRAM 1000 also has a pre-fetch decoder 1004 connected to the address buffer 102 for receiving column addresses (A0-A8) and controlling multiple selections of the column selective lines. The 16M-bit DRAM 1000 further includes a pre-decoder 105 connected to the pre-fetch decoder 1004 and a column decoder 106 also connected to the pre-fetch decoder 1004. The pre-decoder 105 and the column decoder 106 are connected to each other. The column decoder 106 is connected through a sense amplifier 114 to the memory cell array 101. The 16M-bit DRAM 1000 further includes a clock generator 107 for generating clock signals to control the timings of the pre-fetch decoder 1004 The sense amplifier 114 is connected through a latch circuit 111 to an input/output switch 108. The input/output switch 108 is connected to an output buffer 109 and an input buffer 110.
The read out operation is made as follows. The address buffer 102 receives input addresses A0-A11 as row addresses to supply the received row addresses A0-A11 to the row decoder 103 and also to supply the received addresses A0-A8 as column addresses to the pre-fetch decoder 1004.
The row decoder 103 then decodes the received row addresses A0-A11 to select one of the 4096 word lines in accordance with the decoded row addresses A0-A11. The pre-fetch decoder 1004 supplies YAD3-YAD8 as higher bits of the column addresses A0-A8 to the pre-decoder 105 and also pre-decode the lower bits A0-A2 to output pre-decoded addresses Y0-Y7. The operations of the pre-fetch decoder 1004 are controlled by signals LOAD0, LOAD1, LOAD2, COUNT and COUNT2 supplied from the clock generator 107. LOAD0 is a signal generated by the clock generator 107 in response to rising of a clock signal CLK from an external device. LOAD1 and LOAD2 are signals generated in synchronizes with the clock signals CLK when the signals supplied from external device are write command and read command.
COUNT and COUNT2 are signals generated in correspondence to the burst length after LOAD1 and LOAD2 have been generated. Although the clock generator generates other control signals, those control signals are not relative to the present invention, for which reason the descriptions about those signals will be emitted.
The decoded signals outputted from the pre-decoder 105 and the pre-decoded address from the pre-fetch decoder 1004 are supplied to the column decoder 106 whereby the column decoder 106 can select the column selective line CSL.
The above pre-fetch decoder 1004 receives burst signals B4 and B8 which indicate the burst lengths so that the pre-fetch decoder 1004 can, in accordance with those received burst signals B4 and B8, output pre-decode addresses where two bits of those addresses are in the active level, so as to select an address corresponding to the input address and another address of data to be outputted subsequently. The column decoder 106, therefore, receives the decoded signals outputted from the pre-decoder 105 and the pre-decode addresses having two bits being in the active level whereby the two column selective lines are concurrently selected.
The 16M-bit DRAM 1000 in addition includes an even address redundancy decoder 1112 and an odd address redundancy decoder 1113, both of which operate to substitute a defective memory cell with redundancy memory when an address of the defective memory cell is selected, for those purpose each of the even address redundancy decoder 1112 and the odd address redundancy decoder 1113 is connected to the pre-fetch decoder 1004 and also connected through the sense amplifier 114 to the memory cell array 101. Each of the even address redundancy decoder 1112 and the odd address redundancy decoder 1113 have been programmed by fuse-trimming so as to judge whether or not the address for input is an address to be substituted. If the address is to be substituted, then inhibition signals RED0 and RED1 are generated to inhibit selection of the column selective line and further redundancy column selective lines RYS0 and RYS1 are activated to select redundancy cells.
The even address redundancy decoder 1112 receives inputs of YAD3-YAD8 as the lower bits of the column addresses and also receives inputs of even pre-decode pre-addresses Y0P, Y2P, Y4P and Y6P as the pre-decoded lower bits A0-A2, whilst the odd address redundancy decoder 1113 receives inputs of YAD3-YAD8 as the lower bits of the column addresses and also receives inputs of odd pre-decode pre-addresses Y01P, Y3P, Y5P and Y7P as the pre-decoded lower bits A0-A2.
Since each of the column selective lines CSL is connected to eight memory cells as described above, if two column selective lines CLS are selected, this means that data stored in the sixteen memory cells are concurrently read out as 16-bit data.
The read out 16-bit data are then latched by the latch circuit 111 before those data are supplied to the input/output switch 108.
Further, the pre-fetch decoder 1004 supplies the input/output switch 108 with a signal CI0 which designates which column selective line should be read-out operated to read out data from memory cells connected to the indicated one of the column selective lines, so that the input/output switch 108 selects latched data from the memory cells connected to the designated one of the column selective lines in accordance with the CI0 signal prior to outputting the selected data to the output buffer 109.
The above read-out operation of cell data is made if the redundancy column selective lines RYS0 and RYS1 are selected in place of the column selective lines CSL inhibited to be activated.
The output buffer 109 outputs the data as output data D0-D7 of the 16M-bit DRAM. During the output of the output data D0-D7 from the output buffer 109, the pre-decode address is changed in accordance with the COUNT2 signal from the clock generator 107 to select other column selective line for read-out operations.
The outlines of the operations of the 16M-bit DRAM are as described above. The subsequent descriptions will focus on operation of the individual elements of the 16M-bit DRAM.
FIG. 2 is a circuit diagram illustrative of circuit configurations of the pre-fetch decoder 1004 in the conventional 16M-bit DRAM. The pre-fetch decoder 1004 comprises an address latch generator block 280 and a pre-decode block 290.
The address latch generator block 280 receives the column addresses A0-A8 and generates internal address signals YAD0-YAD2 based upon the lower bits A0-A2 and also generates internal address signals YAD3-YAD8 based upon the higher bits A3-A8 which are, however, represented by "Ai" in FIG. 2.
The pre-decode block 290 receives the internal address signals YAD0-YAD2 to generate pre-decode addresses Y0-Y7 and pre-decode pre-addresses Y0P-Y7P. The pre-decode block 290 has latch circuits 600-602 and a selective signal generator circuit 603.
The latch circuit 600 comprises nine latch circuits 600-0 through 600-8 wherein the latch circuits 600-3 through 600-8 receive the column addresses A3-A8 respectively. In FIG. 2, the latch circuits 600-3 through 600-8 are represented by "600-i". Also the latch circuit 601 comprises nine latch circuits 601-0 through 601-8 wherein the latch circuits 601-3 through 601-8 receive the column addresses A3-A8 from the latch circuits 600-3 through 600-8 respectively. In FIG. 2, the latch circuits 601-3 through 601-8 are represented by "601-i".
The latch circuits 600, 601 and 602 fetch data after the LOAD0 signal, the LOAD1 signal and the LOAD2 signal have been activated respectively.
The latch circuits 602-1 and 602-2 are supplied with the COUNT2 signal so that integrated counter circuits perform count-up operations, in response to the COUNT2 signal, of address data A1 and A2 fetched in response to the activation of the LOAD2 signal.
The burst signal B8 is a signal which indicates that the burst length is "8" in high level "1". When the burst signal B8 is in high level, a carry from the latch circuit 602-1 to 602-2 or from A1 to A2 is made in accordance with the logic with reference to output signals INT1 from the latch circuit 602-1.
Also the burst signal B4 is a signal which indicates that the burst length is "4" in high level "1". If the burst signals B4 and B8 are in the low level, then this means that the burst length is "2".
The selective signal generator circuit 603 is supplied with the COUNT signal so that data stored in the selective signal generator circuit 603 are inverted whenever the COUNT signal is activated.
FIG. 3 is a circuit diagram illustrative of a circuit configuration of a column decoder in the conventional 16M-bit DRAM. The column decoder 106 comprises 64 switch circuits 106-0 through 106-63, each of which is commonly supplied with the pre-decode addresses Y0-Y7 from the pre-fetch decoder 1004 as well as supplied with decoded signals outputted from the pre-decoder 105.
FIG. 4 is a fragmentary circuit diagram illustrative of a circuit configuration of a pre-decoder 105 in the conventional 16M-bit DRAM. YADX and YADY mean column addresses YAD3 and YAD4 or YAD5 and YAD6 or YAD7 and YAD8. The three sets of the column addresses are decoded into AX0AY0, AX1AY0, AX0AY1 and AX1AY1. The decoded signals are then inputted into the column decoder 106 so that the column decoder 106 receives both those decoded signals and the pre-decode addresses Y0-Y7 to select the column selective line CSL.
FIG. 5 is a circuit diagram illustrative of a circuit configuration of a switch circuit 106-k in the column decoder 106 in the conventional 16M-bit DRAM. The switch circuit 106-k has p-channel MOS transistors 1500-1503 and 1507 as well as n-channel MOS transistors 1504-1506 and 1509.
Decoded signals A3xA4y, A5xA6y, A7xA8y from the pre-decoder 105 are inputted into gates of the transistors 1502, 1504, and gates of the transistors 1501 and 1505 as well as gates of the transistors 1500 and 1506. When the decoded signals A3xA4y, A5xA6y, A7xA8y are activated into high level "1" the n-channel MOS transistors 1504 and 1506 turn ON so that a line 1530 has a potential of Vss(0).
As a result, the pre-decode addresses Y0-Y7 are outputted through buffer circuits 1521-0 through 1521-7 respectively.
When at least one of the decode outputs A3xA4y, A5xA6y, A7xA8y is in low level "0", then the buffer circuits 1521-0 through 1521-7 output "0".
FIG. 6 is a circuit diagram illustrative of a circuit configuration of the even address redundancy decoder circuit 1112 in the conventional 16M-bit DRAM. In the even address redundancy decoder circuit 1112, programming is made for even address to be substituted where the lowest bit YAD0 of the column address is "0". The even address redundancy decoder circuit 1112 has fuse elements 1200-0 through 1200-15 cut by laser trimming so that programming of the address to be substituted is made.
The fuses 1200-4 through 1200-15 are used for programming of the lower bits YAD3-YAD8 of the column address. The fuses 1200-4 through 1200-15 are connected to drains of the n-channel MOS transistors 1201-4 through 1201-15 whose gates are applied with the corresponding address signals or inverted signals thereof, so that if the address logic is "1" corresponding to the substituting address YAD3, then the fuse 1200-5 is cut. If the address logic is "0", then the fuse 1200-4 is cut. The programming for the addresses YAD4-YAD8 are executed similarly.
The fuses 1200-0 through 1200-3 are used for programming of the lower bits YAD0-YAD2 of the column address. The fuse 1200-0 through 1200-3 are respectively connected to drains of the n-channel MOS transistors 1201-0 through 1201-3 whose gates are applied with re-decode pre-addresses Y0P, Y2P, Y4P and Y6P so that if the lower bit of the column address corresponds to the substituting address Y0P, then the fuse 1201-0 is cut. The programming for the addresses Y2P, Y4P and Y6P are executed similarly.
A signal PRE is a pre-charge signal generated by the clock generator 107 in response to the variation of the internal address signal. The low level corresponds to the active level which causes the p-channel transistor 1219 to turn ON for judging of substituting address to the input of the new column address signals YAD0-YAD8.
If the address signals YAD3-YAD8 inputted into the even address redundancy decoder 1112 and the pre-decode pre-addresses Y0P, Y12P, Y4P and Y6P correspond to the addresses to be substituted, then the fuses corresponding to the logic value of the respective address bits are cut whereby a current path for discharging the line 1220 turns OFF.
The line 1220 is therefore charged into high level so that the selective signal RED0 for inhibiting selection of the column selective line becomes low level whilst the redundancy selective line RYS0 becomes high level.
If, however, address signals YAD3-YAD8 inputted into the even address redundancy decoder 1112 and the pre-decode pre-addresses Y0P, Y12P, Y4P and Y6P do not correspond to the addresses to be substituted, then the fuse corresponding to any of the address bits is not cut and the current path for discharging the line 1220 remains ON, for which reason the signal PRE is unable to charge the line 1220 and the line 1220 is in the low level. The selective signal RBD0 for inhibiting selection of the column selective line becomes high level whilst the redundancy selective line RYS0 becomes low level.
FIG. 7 is a circuit diagram illustrative of a circuit configuration of the odd address redundancy decoder circuit 1113 in the conventional 16M-bit DRAM. In the odd address redundancy decoder circuit 1113, programming is made for odd address to be substituted where the lowest bit YAD0 of the column address is "1" to control signals RED1 inhibiting selections of the column selective line and redundancy column selective line RYS1 selecting the redundancy cell.
FIG. 8 is a circuit diagram illustrative of a circuit connection of the column selective lines, the redundancy column selective lines RYS0 and RYS1 and bit lines. Each of the column selective line is connected only a pair of the bit lines. The adjacent pairs of the bit lines are connected to either different I/O buses 1600 and 1601 alternately.
For the 2-bit pre-fetch, the paired bit lines connected to one of the I/O buses 1600 and 1601 are selected so that 2-bit data are latched by the latch circuit.
The redundancy column selective lines RYS0 and RYS1 are connected to pairs of the bit lines respectively and connected to the different I/O buses 1600 and 1601 respectively. The redundancy column selective line RYS0 is for CSL8k, CSL8k+2, CSL8k+4, and CSL8k+6 whilst the redundancy column selective line RYS1 is for CSL8k+1, CSL8k+3, CSL8k+5, and CSL8k+7. Since actually the data width is "8", eight input/output terminals are provided. Nevertheless, only two pairs of the input/output buses 1600 and 1601 are illustrated in FIG. 8 although the sixteen pairs of the input/output buses are provided actually. In FIG. 8, the column selective line is connected to only one pair of the bit lines, even actually the column selective line is further connected to bit lines connected to other input/output buses so that the column selective line is connected to the eight pairs of the bit lines.
With reference back to FIG. 2, the read out operations will be described to focus on the operations of the pre-fetch decoder 1004 assuming that input addresses A2, A1 and A0 are "0", "1" and "1" whenever the burst length is 2, 4 or 8.
When the burst length is 2, the read out operation will be described with reference to FIGS. 2 and 23.
The column addresses A0-A8 supplied from the address buffer 102 are latched by the latch circuit 600 in response to the LOAD0 signal. Namely, the addresses A2, A1 and A0 are latched in the latch circuits 600-2, 600-1 and 600-0 to store "0", "1" and "1" respectively so that "0", "1" and "1" are supplied to the internal address signals IA2, IA1 and IA0 Read command of combinations of chip select (SCB), row address strobe (RASB), column address strobe (CASB) and write enable (WEB) s supplied whereby the signal LOAD0 and LOAD1 are activated so that the internal address signals IA0-IAi are latched by the latch circuits 601, 602 and 603 in accordance with LOAD1.
FIG. 9 is a circuit diagram illustrative of a circuit configuration of latch circuit 601-0.
Since the burst signals B4 and B8 are "0", then output form an OR-gate 700 is "0", for which reason even if the signal LOAD1 is activated, then YAD0 remains "0".
Logic "1" of the internal address signal is supplied to an output INT0 in accordance with the LOAD1. Logic "1" of the INTA0 is stored in he selective signal generator circuit 603 in accordance with the LOAD2.
FIG. 10 is a circuit diagram illustrative of a circuit configuration of latch circuits 601-1 and 602-1. Logic "1" of the internal address signal IA1 is stored in the latch circuits 601-1 and 602-1 in accordance with LOAD1 and LOAD2 whereby logic "1" is supplied to the column address signal YAD1.
FIG. 11 is a circuit diagram illustrative of a circuit configuration of latch circuits 601-2 and 602-2. Logic "0" of the internal address signal IA2 is stored in the latch circuits 601-2 and 602-2 in accordance with LOAD1 and LOAD2 whereby logic "0" is supplied to the column address signal YAD2.
In the pre-fetch decoder 1004, since the burst signals B4 and B8 are "0", the switches 629 and 630 are in OFF and the nodes 633 and 634 remains "1".
As described above, since the signals "YAD2, YAD1 and YAD0 are supplied with "0", "1" and "0", the pre-decode addresses Y2P and Y3P are "1" and the remaining pre-decode addresses are "0".
Whether the pre-decode address is a substituting address or not is judged by the even address redundancy decoder 1112 and the odd address redundancy decoder 1113.
If the pre-decode address is the substituting address, then the signal RED0 or RED1 is "0" and further the pre-decode addresses Y0, Y2, Y4 and Y6 or Y1, Y3, Y5 and Y7 are "1".
Since the pre-decode address is activated by logic "0", the selection of the column selective address is inhibited.
If, however, the pre-decode address is not the substituting address, then signals RED0 and RED1 are "1" and the pre-decode addresses Y2 and Y3 are "0" and the remaining pre-decode addresses are "1".
In accordance with the pre-decode addresses, the corresponding column selective lines or RYS0 and RYS1 are selected so that 16-bit data are latched in the latch circuit and then supplied to the input/output switch 108.
Since the selective signal CIO is "1", 8-bit data are selected from the selected column selective line corresponding to Y3P of the pre-decode addresses or 8-bit data read out in accordance with RYS1 are selected to be supplied to the output buffer 109.
When the burst length is 2, after the LOAD1 signal has been generated, the COUNT signal is generated by the clock generator 107 in synchronization with the clock signals.
In accordance with the COUNT signal, the selective signal CIO is inverted into "0" so that 8-bit data are selected from the column selective line corresponding to the signal Y2P of the pre-decode address or 8-bit data read out in accordance with the RYS0 are selected to be supplied to the output buffer 109.
As a result, the output of data are made in the order of " . . . 011"(=3), " . . . 010"(=2).
When the burst length is 4, the read out operation will be described with reference to FIGS. 2 and 24. In this case, the burst signal B4 is "1" and the burst signal B8 is "0".The switches 629 and 631 are in ON and the switches 630 and 632 are in OFF.
In the latch circuit 601-0, since the burst signal B4 is "1", the logic "1" of the internal address signal IA0 is supplied to the column address signal YAD0. The selective signal generator circuit 603 and other latch circuits store the same data as when the burst length is "2".
The pre-decode addresses Y0P and Y3p are "1" and the others are "0". Similarly when the burst length is 2, the pre-decode addresses are judged to be substituted or not by the even address redundancy decoder 1112 and the odd address redundancy decoder 1113 to decide high or low level of the RED0, RED1, RYS0 and RYS1.
Data read out by the pre-decode addresses are latched by the latch circuits. In accordance with the signal CIO supplied to the input/output switch 108, data from the column selective line CSL corresponding to the pre-decode address Y3P are selected or 8-bit data read out from the redundancy column selective line RYS1 are selected for supply to the output buffer 109.
After the LOAD1 and LOAD2 signals are been generated, the signal COUNT is generated tree times by the clock generator circuit 107 in synchronization with the clock signals wherein after 2 clocks have been supplied, the signal COUNT2 is generated one time.
When the COUNT signal is generated one time, the selective signal CIO is inverted into "0" so that the output is changed into the data from the column selective line CSL corresponding to the pre-decode address Y3P or 8-bit data read out from the redundancy column selective line RYS1.
Subsequently when the signals COUNT and COUNT2 are generated, the logic YAD1 is inverted into "0" by a flip-flop circuit 840 in the latch circuit 602-1.
In the latch circuit 602-2, the burst signal B8 is "0" , for which reason the output of the AND-gate 926 is "0" and the logic of the YAD2 is not inverted.
As a result, the pre-decode addresses Y1P and Y2P are "1" and the others are "0". In this case, the selective signal CIO is inverted two times and returned into "1", for which reason the input/output switch 108 selects the data from the column selective line CSL corresponding to the pre-decode address Y1P or 8-bit data read out from the redundancy column selective line RYS1.
The final signal COUNT has been generated, the selective signal CIO is inverted into "0". The input/output switch 108 selects the data from the column selective line CSL corresponding to the pre-decode address Y2P or 8-bit data read out from the redundancy column selective line RYS0.
Consequently, first the pre-decode addresses Y0P and Y3P are "1", and then when the COUNT2 is generated, then the pre-decode addresses Y1P and Y2P are "1".
Data read out from the column selective line corresponding to the Y3P are first supplied to the output buffer 109. Every when the signal COUNT is generated, data read out from the column selective lines corresponding to the Y0P, Y1P and Y2P are supplied to the output buffer 109.
In view of the column address, data are outputted in the order of " . . . 011"(=3), " . . . 000"(=0), " . . . 001"(=1), " . . . 010"(=2).
When the burst length is 8, the burst signal B8 is "1". The switches 629 and 631 are OFF whilst the switches 630 and 632 are in ON. The pre-decode addresses Y3P and Y4P are "1" and the others are "0".
When the logic of the internal address signal INT1 is "1", the logic of the YAD2 is also inverted in response to the generation of the COUNT2 signal by the latch circuit 602-2 for counting up operations.
After the LOAD1 and LOAD2 signals have been generated, the signal COUNT is generated seven times by the clock generator circuit 107 in synchronization with the clock signals. The COUNT2 signal is generated three times every two clocks. The pre-decode address is made into "1" every when the COUNT2 signal is generated, for which reason the pre-decode addresses are changed in the order of Y5P and Y6P, Y7P and Y8P and Y0P and Y1P.
Data read out from the column selective line corresponding to Y3P are first supplied to the output buffer 109. Every when the COUNT signal is generated, data read out from the column selective limes corresponding to Y4P, Y5P, Y6P, Y7P, Y0P, Y1P, Y2P are supplied to the output buffer 109.
In view of the column address, data are outputted in the order of " . . . 011"(=3), " . . . 100"(=4), " . . . 101"(=5), " . . . 110"(=6), " . . . 111"(=7), " . . . 000"(=0), " . . . 001"(=1), " . . . 010"(=2).
FIG. 12 is a table indicating how the pre-decode pre-addresses are outputted by the pre-fetch pre-decoder 1004 in accordance with the input addresses A0-A8. The pre-decoder pre-address on the table means address of the logic "1".
In the above conventional system, the address signals which should be first read out are supplied to the pre-fetch pre-decoder 1004 for receipt of the burst length information to generate address signals which should be concurrently read out, each of which is combination of even address and odd address. The combination is decided in accordance with the burst length.
Whether or not the each address is to be substituted is judged by the even address redundancy decoder and the odd address redundancy decoder in accordance with the pre-decode signals from the pre-fetch pre-decoder.
FIG. 13 is a timing chart of pre-decode pre-address and the pre-decode address for selecting the column selective line CSL when the input addresses A2, A1 and A0 are "0", "1", and "1"(=3) and the burst length is 4.
When the address signals YAD2, YAD1 and YAD0 are supplied, the pre-decode addresses Y3P and Y0P are "1", provided that the even address corresponding to the Y0P is a substituting address and the odd address has been substituted in the former step where the Y1P was selected and the odd address corresponding to the Y3p is not substituting address.
When the Y0P comes "1", the pre-decode signal Y0 is once activated into "0" before the substituting address is recognized by the even address redundancy decoder whereby the inhibition signal for inhibiting selection of the column selective line becomes "0" so that Y0 is returned into "1".
When the Y3P becomes "1", the substituting address is recognized by the odd address redundancy decoder whereby the inhibition signal for inhibiting selection of the column selective line becomes "1" so that Y3 is activated into "0".
In order to finalize the pre-decode signal for selecting the column selective line, it takes a time to generate the judgement signal by the redundancy decoder after the pre-decode pre-address has been generated.
The above necessary time is in the range of 1-2 nanoseconds in the DRAMs currently on the development. This causes a timing delay to limit the access speeds.